March Meet'n Learn Meeting Details

This will be a joint meeting with the LA/OC SMTA Chapter.
Come out and Network with Industry Colleagues.

DATE
Tuesday, March 26th, 2024

COST
The cost to attend this event will be $0.
A great opportunity to check out what a PCEA or SMTA membership is about.
We are pleased to have Siemens Digital Industries Software Sponsorship of our event by helping us with the venue.
(Dinner provided = Pizza and salad with ice tea or water)

TIME
6:00pm to 8:00pm PDT

AGENDA
Arrive and grab your badge and food 6:00pm
PCEA/SMTA update and introductions 6:30pm - 6:45pm
Speaker presentation 6:45pm - 7:45pm
Q & A discussion 7:45pm - 8:00pm

LOCATION
The Met
535 Anton Blvd.
Costa Mesa, CA 92626
Ground Floor Conference Room
(Parking in Starbucks Parking Lot)

Presentation
Learn the benefits of understanding PCB design Standards.

Topic
What's New in IPC-6012 Revision F (Part II)

SPEAKER
Gerry Partida
Vice President of Technology
Summit Interconnect

ABSTRACT
Join us for this informative discussion to review a few of the recent changes and their potential impact on your next PCB designs.

Topics to be covered:
Printed Board Cavities (3.3.10)
Evidence of Etchback (3.6.2.6.1)
Total Copper Penetration / Evaluation of Etchback (3.6.2.6.2)
Dimples and Protrusions (3.6.2.11.3)
Plated Internal Layers (3.6.2.14.1)
Minimum Dielectric Spacing (3.6.2.18.1)

Gerry’s insights are based on 38+ years in the PCB industry. He is the Co-Chair of IPC-6012/IPC-A-600 and committee member with IPC-6018, IPC-1601, IPC-2221, IPC-2222 and other standard committees.

RESERVATIONS
https://smta.org/events/EventDetails.aspx?id=1845587&group=225197&mc_cid=5928642ccb
Reserve a spot on your calendar for Tuesday, March 26th from 6:00pm to 8:00 pm for this educational “Meet‘n Learn” event.

Don't miss out on this educational “Meet‘n Learn” event!

We look forward to seeing you at our PCEA & LA/OC SMTA joint meeting live event…!

If you have not already joined PCEA, we’d love to have you sign up to become a member by clicking here. Although it’s free to join, we encourage you to donate if you can. As a non-profit organization, your donations make a difference in helping us create new chapters, acquire talented speakers, improve the website and provide better educational content.

February Lunch 'n Learn Meeting Details

DATE
Thursday, February 23rd, 2023

COST
The cost to attend this Lunch 'n Learn event will be $15.00 at the door.
We are pleased to have Siemens EDA and Freedom CAD’s Sponsorship of our event by helping us with the cost of the venue expense.
(lunch provided = sandwich, fruit cup, chips, cookie with iced tea or ice water)

TIME
11:30am to 1:30pm PDT

AGENDA
Arrive and grab your badge and lunch 11:30
PCEA update and introductions 11:45 - 11:55
Speaker presentations 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Raffle for $1000.00 in Door prizes 1:25 - 1:30

LOCATION
Santa Ana Elks Lodge
"Emerald Room"
1751 S. Lyon Street
Santa Ana, CA 92705
Map Link to meeting location with plenty of free parking

PCB Professionals - For our next Lunch ‘n Learn event, we will explore the advances in the technology of embedding resistors and capacitors which can benefit many designs today. We have two guest speakers who will make informative presentations to educate us on this important and growing technology trend.
– Scott McCurdy

Presentation
Embedded Passives
Learn the benefits of designing with internal resistors and capacitors

Topic #1
Embedded Capacitance and Improved Power Delivery

SPEAKER #1
Bob Carter
VP-Business Development & Technology
Oak-Mitsui Technologies

ABSTRACT #1
This presentation provides an overview/definition of the different types of embedded capacitance as well as fundamentals of power distribution network design for high-speed digital circuits. Bob will also cover how it is used in various types of practical applications such as MEM’s and RF modules. Using ultra-thin power and ground plane pairs as embedded capacitance layers provide superb electrical performance with regards to charge delivery. There are particular benefits for reducing or mitigating noise and improving logic transitions. Performance, manufacturability, reliability and cost analysis will be discussed.

TOPIC #2
Designing with TCR® Thin-Film Embedded Resistor Foil

SPEAKER #2
John Andresakis
Business Development Director
Quantic OhmegaGerry Partida

ABSTRACT #2
John will present an overview of thin film embedded resistors and educate us on the applications showing the advantages and reliability by designing with this technology. Improvements in signal integrity can be achieved and embedded resistors can eliminate many SMT components to free up surface space while improving performance and reliability. We will learn about power handling of embedded resistors to aid in thermal management. Designers will learn about the various types of designs, including RF and Microwave applications, which can greatly benefit from adopting embedded resistor technology.

RESERVATIONS
Reserve a spot on your calendar for Thursday, February 23rd from 11:30 am to 1:30 pm for this educational “Lunch ‘n Learn” meeting event.

Don't miss out on this educational “Lunch ‘n Learn” event!

Please RSVP to scott.mccurdy@freedomcad.com no later than
noon Wednesday, February 22nd, so we can get an accurate headcount for the luncheon.

We look forward to seeing you at our live event…!

If you have not already joined PCEA, we’d love to have you sign up to become a member by clicking here. Although it’s free to join, we encourage you to donate if you can. As a non-profit organization, your donations make a difference in helping us create new chapters, acquire talented speakers, improve the website and provide better educational content.

October Lunch 'n Learn Meeting Details
second in-person meeting event in 2½ years

DATE
Wednesday, October 19th, 2022

COST
The cost to attend this Lunch 'n Learn event will be $15.00 at the door.
We are pleased to have Siemens EDA and Freedom CAD’s Sponsorship of our event by helping us with the cost of the venue expense.
(lunch provided = sandwich, fruit cup, chips, cookie with iced tea or ice water)

TIME
11:30am to 1:30pm PDT

AGENDA
Arrive and grab your badge and lunch 11:30
PCEA update and introductions 11:45 - 11:55
Speaker presentations 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Raffle for $1000.00 in Door prizes 1:25 - 1:30

LOCATION
Santa Ana Elks Lodge
"Emerald Room"
1751 S. Lyon Street
Santa Ana, CA 92705
Map Link to meeting location with plenty of free parking

PCB Professionals - This will be our 2nd in-person Lunch ‘n Learn meeting at the beautiful new Elks Lodge in Santa Ana. We will have 2 knowledgeable speakers presenting an educational and entertaining dialog you won’t want to miss.
– Scott McCurdy

Presentation
Best Practices for Design Success
An eye-opening dialog between a Designer and a Fabricator

SPEAKER #1
Stephen Chavez, MIT, CPCD, CID+
Sr. Product Market Manager
Siemens EDA
and Chairman of the Printed Circuit Engineering Association

SPEAKER #2
Gerry Partida
Vice President of Technology
Summit Interconnect

Click here to stream the video

Click here for their Slide presentation

ABSTRACT
PCB designers just don’t simply “connect the dots” or “push the magic button,” as some may suggest. They design complex PCBs that contain physical packages smaller than ever before while addressing electrical, mechanical, and thermal variables and cost. Success in PCB design means knowing and understanding what you are doing and how the decisions you make and implement upstream impact downstream ramifications.

There are key factors in achieving success in PCB design. In this presentation our speakers will focus on the relationship between design and fabrication. We’ll discuss industry best practices within the design to fabrication process, along with the pros and cons that affect ROI when best practice recipes are implemented and when they are not implemented (the cost of doing nothing).

With today’s EDA tools, and eagerness of suppliers offering their technical support, the potential for success is higher than ever. This collaborative approach makes a positive difference in getting it right the first time, reducing re-spins (cost), increasing yields, and ultimately getting to market faster.

What You Will Learn:
Increase productivity and proficiency in PCB design to fab
Capitalize on existing industry best practices of DFM and MFG outputs
How you can reduce cost
A short comedy scenario depicting the dialog between a principal PCB designer and a fabricator

If you have not already joined PCEA, we’d love to have you sign up to become a member by clicking here. Although it’s free to join, we encourage you to donate if you can. As a non-profit organization, your donations make a difference in helping us create new chapters, acquire talented speakers, improve the website and provide better educational content.

July Lunch 'n Learn Meeting Details
first in-person meeting event in 2½ years

DATE
Tuesday, July 26th, 2022

COST
The cost to attend this Lunch 'n Learn event will be $10.00 at the door.
We are pleased to have Insulectro's sponsorship of our event by helping us with the cost of this event.
(lunch provided = sandwich, fruit cup, chips, cookie with iced tea or ice water)

TIME
11:30am to 1:30pm PDT

AGENDA
Arrive and grab your badge and lunch 11:30
PCEA update and introductions 11:45 - 11:55
Speaker presentations 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Raffle for Door prizes 1:25 - 1:30

LOCATION
Santa Ana Elks Lodge
"Emerald Room"
1751 S. Lyon Street
Santa Ana, CA 92705

PCB Professionals - This will be our first in-person meeting event in 2½ years, and we are pleased to have Insulectro sponsor our Lunch 'n Learn meeting at the beautiful new Elks Lodge in Santa Ana. We will have 3 knowledgeable speakers for our audience to educate you and interact with your questions.
– Scott McCurdy

Presentation
Topic #1: Signal Integrity Applications in Layout
SPEAKER
Mike Creeden, CID+
Master Inst. PCE-Edu
Technical Director - Design Education
Insulectro
ABSTRACT
Mike will talk about applying SI theory to your layout, covering EM fields, laminates, copper profile, uninterrupted GND return Path, impedance discontinuities from your routing, and proper shielding.

Slide presentation - click HERE Link to YouTube video - click HERE

Topic #2: Advanced Via Solutions using Ormet® Pastes
Chris Hunrath
Vice President of Technology
Insulectro
ABSTRACT
Chis will present Z-Axis Interconnects for Multi-lam HDI, Back-drill elimination, solving high aspect ratio plating on high layer count boards, and any-layer-via usage.

Slide presentation - click HERE Link to YouTube video - click HERE

Topic #3: Overcoming Flex Design Challenges
Geoffrey Leeds
CID Flex Product Manager
Insulectro
ABSTRACT
Geoffrey will talk about overcoming Flex Design challenges by understanding the Building Blocks; pitfalls to avoid during layout; Dynamic vs. Static design constraint; and the proper materials and their applications.

Slide presentation - click HERE Link to YouTube video - click HERE

If you have not already joined PCEA, we’d love to have you sign up to become a member by clicking here. Although it’s free to join, we encourage you to donate if you can. As a non-profit organization, your donations make a difference in helping us create new chapters, acquire talented speakers, improve the website and provide better educational content.

April Lunch 'n Learn Virtual Meeting Details

DATE
Wednesday, April 20th, 2022

TIME
11:30am to 1:00pm PDT

AGENDA
11:30 - 11:45 - PCEA Update & Introductions
11:45 - 12:45 - Technical Presentation
12:45 - 12:55 - Q&A Discussion
12:55 - 1:00 - Door prize raffle

LOCATION
At your computer via Zoom (while you eat your lunch)

PCB Professionals - We are pleased to have 2 distinguished speakers who are both passionate PCB designers presenting to our audience. They will be covering many of the challenges that companies face with the increasing shortage of talented PCB designers including paths for introducing young people to learn about this career, and ways to educate existing designers to take their knowledge and skill set to a higher level. Also, the importance of mentoring the next generation that might be filling your shoes when you finally retire. – Scott McCurdy

Presentation
Topic #1: It's a Brave New World
Mentoring the Next Generation of Great Designers

SPEAKER
John Watson, CID
Customer Success Manager
Altium

Abstract
In the past couple of years, we all have experienced issues with component shortages. But even more critical has been the shortage of promising PCB talent and great designers to fill the various job openings. In 2005, PCB Magazine warned that Printed Circuit Board designers were retiring from the industry in droves. Unfortunately, the massive sucking sound we now hear is just that. With advancements in our industry at ludicrous speed, we all are experiencing a lack of available talent to meet our company's needs. Also, as PCB designs are more complex, it is vital to bridge the gap for new designers and what they will need to know.

• How do we turn things around?

• How do we develop a passion and hunger for PCB Design?

• What will it take to mentor the next generation?

• How do you tap into resources of Palomar College and the PCEA to improve your team's skills?

Instructing and mentoring the next generation of designers will be crucial to our industry's success. Facing this problem head-on is a partnership between Palomar College and PCEA with a program that reaches out to brand new designers to introduce them to the career of PCB Design. That includes a unique program for High Schools uniting with the school's STEM or Robotic curricula. Furthermore, they are working with PCEA to continue their education. Then come in partnership with companies that need the talent to allow these individuals to get their foot in the door. By investing in the new designers, with instruction and mentoring, the sky is the limit.

Topic #2: The Next Step in Designer Education for Becoming a Great Designer
Exploring the most comprehensive educational course for professional development

Speaker
Mike Creeden, CID+
Technical Director - Design Education
Insulectro

Abstract
The Printed Circuit Engineering Professional curriculum teaches a knowledge base and develops a competency for the profession of printed circuit engineering layout, based on current technology trends. The course references general CAD tool practices, however, it is vendor-agnostic. It also provides ongoing reference material for continued development in the profession.

The 40-hour course was developed by leading experts in printed circuit design with a combined 250 years of industry experience and covers approximately 67 major topics under the following headings: Basics of the profession, materials, manufacturing methods and processes; circuit definition and capture; board layout data and placement; circuit routing and interconnection; signal-integrity and EMI applications; flex PCBs; documentation and manufacturing preparation; and advanced electronics (energy movement in circuits, transmission lines, etc.).

Class flow: Books sent to students prior to an instructor-led review. This is followed by an optional exam with a lifetime certification that is recognized by the PCEA Trade Association.

September Lunch 'n Learn Virtual Meeting Details

DATE
Wednesday, September 1st, 2021

TIME
11:30am to 1:00pm

AGENDA
11:30 - 11:45 - PCEA Update & Introductions
11:45 - 12:45 - Technical Presentation
12:45 - 12:55 - Q&A Discussion
12:55 - 1:00 - Door prize raffle

LOCATION
At your computer via Zoom (while you eat your lunch)

Presentation
We are pleased to have American Standard Circuits as our sponsor for this virtual event and they will be presenting on 2 interesting topics:
Topic #1: Next Gen Line/Space Capability for PCB Designs

SPEAKERs
Anaya Vardya
President & CEO
American Standard Circuits, Inc.

Haris Basit
Chief Executive Officer
Averatek Corp.

John Bushie
Director of Technology
American Standard Circuits, Inc.

Abstract
The need for increasingly complex electronics, combined with the obsolescence of larger component packages, is driving innovation to provide alternatives to the traditional subtractive-etch fabrication process that will provide circuit layers reliably, and repeatedly, with trace sizes of 25 micron or finer.

A new process has been developed to handle cutting edge PCB requirements for products of the future. ASC has licensed Averatek’s A-SAP™ (Averatek Semi-Additive Process) which enables feature sizes of 25 micron (1 mil) and below, opening new possibilities and options for PCB designers to solve complex design issues. This session will provide an overview of the A-SAP™ process and explore Space, Weight and Packaging benefits including:

• Reduced circuit size

• Reduced layer count

• Reduced lamination cycles

• Improved reliability & signal integrity

• Reduced microvia layers

• Increased electronics functionality within existing footprints

Topic #2: An overview of Via Fill
Choosing the right type for your design application

Speaker
John Bushie
Director of Technology
American Standard Circuits, Inc.

Abstract
Many PCBs have requirements for Via Filling yet there are many different options that a designer can chose from depending on their application. Our speaker will present the different types of via fill and plugging methods and describe the pros and cons of the different available options. The types of materials or plating used has an impact on fabrication, so cost implications will be presented with a goal of providing our audience a better understanding of which via filling choice is right for your design project.

May Lunch 'n Learn Virtual Meeting Details

DATE
Wednesday, May 19th, 2021

TIME
11:30am to 1:30pm

AGENDA
11:30 - 11:45 - PCEA Update & Introductions
11:45 - 12:45 - Technical Presentation
12:45 - 12:55 - Q&A Discussion
12:55 - 1:00 - Door prize raffle

LOCATION
At your computer via Zoom (while you eat your lunch)

SPEAKER
Orlen Bates
Sr. Field Applications Engineer
EMA Design Automation

Presentation
Designing for RF - Tips and Tricks from the PCB Pros

It seems almost every product these days needs to have some level of connectivity be it for end user access on their smart phone, connecting with other similar devices, or providing diagnostic data for real-time health monitoring. What all these requirements have in common is you now have RF sensitive circuits that you need to manage. Learn some quick tips and tricks to help you design and manage RF circuitry in your PCBs.

What You Will Learn:
Best practices to use when designing with RF signals
Common RF design pitfalls and how to avoid them
Questions you should ask when working on RF circuits
Strategies to mitigate RF interference and when to use them

To stream the video of the presentation at our event, click Below:
https://www.youtube.com/watch?v=EIW1Vp7etQk

To view/listen to the question & answer session that followed the presentation, click Below:
https://www.youtube.com/watch?v=NLQzKkz05Kg

December Lunch 'n Learn Virtual Meeting Details

DATE
Wednesday, December 2nd, 2020

TIME
11:30am to 1:30pm

AGENDA
11:30 - 11:45 - PCEA Update & Introductions
11:45 - 12:45 - Technical Presentation
12:45 - 12:55 - Q&A Discussion
12:55 - 1:00 - Door prize raffle

LOCATION
At your computer via Zoom (while you eat your lunch)

SPEAKERs
Amit Bahl
Director of Sales & Marketing
Sierra Circuits
&
Atar Mittal, BSEE
General Manager of the Design and Assembly Division
Sierra Circuits

Presentation
Achieve Optimal Stack-up Design Considering Process and Electrical Performance
Optimize your stack-up from a fabricator’s perspective

Choosing the right materials and the stack-up design for your PCB design project is important because the materials you choose can impact the overall performance. Therefore, understanding the manufacturing process and your options are critical to design success. Knowing how the electrical properties impact your design prior to the manufacturing stage can save you time and money, while achieving optimum results. Understanding how the decisions you make in planning your stack-up affects the electrical performance, manufacturability, and cost of your design is critical. Join us to learn how to improve your stack-up for your next design with this knowledge.

What You Will Learn:
PCB material selection best practices for manufacturability and high-speed performance.
Materials suitable for sequential lamination (HDI)
How to optimize your PCB stack-up for cost, manufacturability, and performance
Creating via structures suitable for HDI
PCB stack-up examples and why they have been designed the way they have

Janary Lunch 'n Learn Meeting Details

DATE
Tuesday, January 21st, 2020

TIME
11:30am – 1:30pm

AGENDA
Lunch served 11:30 - 11:50
Misc. Business 11:45 - 12:00
Presentations 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Door prize raffle 1:25 - 1:30

COST
$10.00
We are pleased to Announce Our Sponsor,

which helps offset venue cost.
If your company would be interested in hosting an event please contact Scott.

LOCATION
Harvard Community Park
14701 Harvard Ave.
Irvine, CA 92606

Driving Directions


SPEAKER
Gerry Partida
Senior Field Applications Engineer
Summit Interconnect

Presentation
Microvias: Have you designed for Reliability?
How to detect weak microvias and avoid costly assembly defects and customer field failures

Gerry’s presentation will review concerns and reliability testing of microvias. He will provide an overview of the HDI processes and present the use of current test methods and the superiority of testing with IPC-D-coupon and IPC-TM-650 test methods 2.6.7.2 and 2.6.27. He will discuss the warning statement in the forthcoming IPC-6012E, Qualification and Performance Specification for Rigid Printed Boards.

Click below to stream the video of Gerry giving his presentation at our event:
https://www.youtube.com/watch?v=rLsGL8KOtQY

July Lunch 'n Learn Meeting Details

DATE
Thursday, July 18th, 2019

TIME
11:30am – 1:30pm

AGENDA
Lunch served 11:30 - 11:50
Misc. Business 11:45 - 12:00
Presentations 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Door prize raffle 1:25 - 1:30

COST
$15.00
We are pleased to have

Altium's sponsorship of our event
by helping us with the cost of the luncheon.

LOCATION
NOTE: special location for this meeting…!
JT Schmid's Restaurant & Brewery
(in Regan’s Room)
2610 E. Katella Avenue
Anaheim, California 92806
714.634.9200
http://www.jtschmids.com/

Driving Directions
(Across from the Honda Center)

Parking Map

SPEAKER
Julie Ellis
Field Applications Engineer
TTM Technologies, Inc.

Presentation
How Fabrication Processes Determine DFM Guidelines
A detailed look at fabrication realities to help you understand capabilities and tradeoffs

Julie will define key fabricator concerns caused by the interplay between material and process tolerances and how they stack up. The end results are minimum DFM guidelines that will generate the highest yields at the fabricator. Each fabrication site Guidelines are established based on their unique equipment sets. The equipment sets are selected to support different technologies ranging from heavy Cu to micro BGA designs. At the end of this presentation, the designer will understand why different fab sites have different capabilities, as well as how to identify and apply the correct design guidelines relating to Registration, Imaging, Aspect Ratio, Mechanical through-hole, Blind laser microvia, Annular Ring, Mechanical drills, Laser drills, Etching, Plated Layer versus non-plated layer finished Cu thickness and VIPPO (via-in-pad, plated over).

April Lunch 'n Learn Meeting Details

DATE
Thursday, April 25th, 2019

TIME
11:30am – 1:30pm

AGENDA
Lunch served 11:30 - 11:50
Misc. Business 11:45 - 12:00
Presentations 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Door prize raffle 1:25 - 1:30

COST
$10.00

LOCATION
Harvard Community Park
14701 Harvard Ave.
Irvine, CA 92606

Mapquest

SPEAKER
Natasha Baker
CEO & Founder
www.snapeda.com

Presentation
The Top 5 Symbol & Footprint Mistakes that even Professional Engineers Make
Common pitfalls to avoid when creating libraries
When creating libraries, standards are crucial for maintaining consistency, accuracy, and reliability. Yet, even with rigid standards in place, mistakes inevitably creep into such a detail-oriented process.

In this talk, we’ll explore the top 5 mistakes that even professionals make when creating component libraries. Delving far beyond the basics, we'll look at the more gnarly errors that trip up engineers. For example, we all know to double-check our pin mappings, but what about how you’ve interpreted the component’s orientation in the datasheet? Misinterpreting a component's top view for its bottom view is one of the top causes of faulty boards that we see. Drawn from our community of 200,000 engineers, our hope is that these lessons will prevent costly prototype iterations and delays on your next project.

Finally, we’ll explore how to prevent these errors on your next designs. For example, by bringing in more verification into your processes through checklists and other solutions.

SLIDES_How and Why to Build Better Libraries by Natasha Baker of SnapEDA Printed Circuit Engineering Association meeting 4-25-2019

VIDEO_How and Why to Build Better Libraries by Natasha Baker of SnapEDA Printed Circuit Engineering Association meeting 4-25-2019

SPEAKER
Terri Kleekamp, CID
Applications Engineering Manager
Mentor Graphics

Presentation
Best Practices for ECAD Library Development

SLIDES_Best Practices for ECAD Library Development by Terri Kleekamp of Mentor Printed Circuit Engineering Association meeting 4-25-2019


Iconnect007 Event Article
See Pages 58 - 61

January Lunch 'n Learn Meeting Details

DATE
Tuesday, January 22nd, 2019

TIME
11:30am – 1:30pm

AGENDA
Lunch served 11:30 - 11:50
Misc. Business 11:45 - 12:00
Presentations 12:00 - 1:20
Q & A discussion 1:20 - 1:25
Door prize raffle 1:25 - 1:30

COST
$10.00

LOCATION
Harvard Community Park
14701 Harvard Ave.
Irvine, CA 92606

Mapquest

TOPIC #1
Signal integrity effects of different PCB structures

High Speed Structures Slides

High Speed Structures Video

This presentation will discuss the following:
Return path vias for single-ended and differential pairs
How the void around the differential via pair structure effects Signal Integrity
How back-drilling effects Signal Integrity and an Eye diagram
Fiber weave effects
Tabbed routing
Inductive Compensation
ETC as time permits

SPEAKER
John Carney
Application Engineer
Cadence

TOPIC #2
Artificial Intelligence and Machine Learning basics and how it will affect PCB design

This presentation will discuss the following:
Machine Learning vs Artificial intelligence vs Deep Learning.
How a machine “learns”
PCB based examples of different types of Machine Learning .
DARPA’s plans for AI and PCB design
Other examples from industry leaders

SPEAKER
John Carney
Application Engineer
Cadence

TOPIC #1
Addressing the challenges of multi board design
Taking the “big picture” approach to system design
SPEAKER
Chris Carlson, CID
Senior Field Applications Engineer
Altium

As technology becomes more complex and miniaturized, the need for more complex multi board systems arise. Clear lines between layout, mechanical and performance concerns begin to blur, which creates the need for PCB designers to take a more holistic view of the system.

In this presentation, Chris Carlson will discuss the unique and varied challenges that arise when doing multi board system designs. He will review the considerations relative to partitioning the PCB, connection management, connector libraries and planning the layout. He will also discuss mechanical features, managing signals, thermal management, reliability and power and signal integrity. Finally, Carlson will show how to ensure good mechanical fit by making the most of your 3D CAD functionality.

TOPIC #2
Design and Manufacturing Developments to
Lower Insertion Loss & Digital Pair SKEW
What a designer needs to know about meeting 56Gb/s speed challenges
SPEAKER
Norm Berry
Director of Laminate and OEM Marketing
Insulectro

As frequency increases, differential pair SKEW and insertion loss become critical considerations for PCB design and manufacture. Add the ever-increasing complexity of reliable designs, while balancing value / cost performance the manufacturing options become more challenging. The designer needs to be aware of advancements in the base material manufacture and the options available to the fabricator.

Whether we are concerned with the demands of HDI designs with stacked, laser drilled micro VIAs or insertion loss on High Speed Digital backplanes, the base material composite, with low profile copper and a mechanically spread glass reinforcement, has a direct impact. Backplanes operating at 56Gb/s require the integration all these factors and the newly developed manufacturing technologies.

TOPIC #1
Rigid-Flex PCB Design
Practical Tips and Best Practices

Presentation Video

SPEAKER
Vern Wnek
Technical Marketing Engineer
Mentor Graphics

Prior to the advent of rigid-flex PCB’s, when a multi-board product included a flex PCB (or multiple flex PCBs), the flex was usually assigned to a flex design specialist. The flex PCB was designed separately from the rigid PCBs, with physical connectors used to assemble the rigid and flex boards into a product-level design. The flex designer was familiar with stackup and material options along with the best practices for stiffeners and bends. There is after all a certain science to flex design that, when properly applied, can help ensure first-pass success. But how can a traditional rigid PCB designer who is not familiar with flex terminology, processes and requirements ensure a high probability for first-pass success when assigned to a rigid-flex design? As with any new skill, education on terminology and best practices along with access to tools that facilitate and ensure process compliance are key.

During this session we will discuss some of the fundamental best practices and guidelines that a rigid-flex designer will need to become familiar with and adhere to in order to be successful.

TOPIC #2
Flex for 5G - Why Materials Matter
Let’s learn about the newest flexible substrate materials

Bonus_HDI Forum – Crosshatched Ground Plane Flex Study - Jonathan Weldon

Presentation Video

SPEAKER
John Weldon
Principal Investigator
Dupont - Circuit and Industrial Technologies

The recent increase in demand for high frequency flex materials with low dielectric constants and loss tangents has made stark the limitations of some flex circuit materials and obvious the need for new ones. Polyimide based flexible copper clad laminates (FCCL’s) such as Pyralux® maintain the lion’s share of the flex circuit market but have long been perceived as frequency limited with certain undesirable properties at mm-wave frequencies. Concurrently, over the past several years liquid crystal polymer (LCP) has become regarded as the gold standard for high frequency flex material.

This topic will focus on the high frequency demands placed on flex materials in modern 5G applications and discern how traditional polyimide based FCCL systems perform when compared to LCP while also helping to map the design and fabrication trade space for these two materials. Working backward from emerging technologies and applications that require 5G performance, this topic will detail new flexible copper clad laminates based on novel polyimides that improve performance of traditional polyimide based systems.

SPEAKER
John Coonrod
Technical Marketing Manager
Rogers Corporation

PCB’s which are used in high frequency or high speed digital applications have many different variables which can alter the intended performance of the circuit. Some of these variables are related to the high frequency circuit materials, some variables are associated with the circuit design and other variables can be attributed to the PCB fabrication process. Additionally there are interactions between these variables and if the designer is aware of these potential differences, many concerns for PCB electrical performance can be minimized.

John’s presentation will start with an overview of key properties for high frequency laminates, as well as some properties which are less well-known and can be problematic if ignored. Following, will be an overview of insertion loss and many different influences which can impact insertion loss. Some influences are related to the high frequency circuit material, such as dissipation factor and copper surface roughness. The circuit design also plays a role on influencing insertion loss and the impact of final plated finishes on insertion loss will be discussed. Finally impedance will be discussed, with a definition of the hierarchy of the variables that influence impedance. Additionally some examples will be given about how to design signal transition vias with minimal reflections and showing that conductor routing may or may not have much influence on impedance reflections depending on rise times.

TOPIC #1
Embedded Thin Film Resistors
An update on current Applications and Design

SPEAKER
Bruce Mahler
Vice President
Ohmega Technologies, Inc.
One of the PCB Designer's tools is the use of embedded passives. Embedded passives free up routing area, reduce assembly, improve reliability, improve electrical performance and for some designs, reduce the cost of the assembled board. OhmegaPly is an embedded resistive material that has seen growing use in a variety of electronic systems, including high frequency RF circuits, MEMs sensors and heater elements. This presentation will provide an overview of the Thin Film resistor technology including its production, product offerings and characteristics. Examples of current OhmegaPly designs will be reviewed and will be followed by a discussion of future trends for embedded resistors in PCB's.

TOPIC #2
Improving Power Delivery Networks (PDNs) Using Polyimide-based Thin Laminates
What PCB Designers need to know about Buried Capacitance

SPEAKER
Jim-Hyun Hwang
Applications Development Engineer
DuPont
This presentation will provide an overview of the use of thin laminate products (i.e. buried capacitance - a pair of power/ground layer pairs) designed for the power distribution design options. The presentation will discuss the use of both 1-mil and 0.5-mil dielectric laminates and the benefits of each. Buried capacitance layers can reduce the number of decoupling capacitors, free up design space, reduce noise and create higher reliability, along with many other benefits. Example stack-ups from high layer count PCBs used for server and telecommunications equipment will be shared. Also, process challenges at fabricators will be addressed.

TOPIC #1
High Speed DDR4 Memory Design and Power Integrity Analysis
What designers need to know to achieve the best performance with DDR4

SPEAKER
Cuong Nguyen
Field Applications Engineering Manager
EDA Direct

PRESENTATION
DDR4 is an entirely new memory architecture with higher bandwidth, lower power consumption, and higher memory capacity. Incorporating DDR4 memory interfaces in today’s design poses many challenges for both the EE’s as well as the layout engineers. These high speed interfaces require careful considerations in terms of optimizing the electrical signaling between sensitive components and to minimize the noise from high switching activities from the memory devices. Layout constraints must be carefully specified to ensure tight timing alignment for clock and strobe signals. In addition, the Power Distribution Network (PDN) also became more fractured to support the many supplies required by current ASIC and FPGA devices. This, an insufficient decoupling for the supplies, can potentially create more noise, crosstalk, and increase the Electro Magnetic Interference (EMI) in the system.

In this seminar, we will review the DDR4 architecture, routing topologies, signaling protocols, how it can be simulated on the PCB, and how to maximize PDN designs from a layout perspective. Based on the simulation results, optimizing trace routing, board stackup, component placements, connectors, terminations, as well as other tradeoffs can be implemented to maximize the performance of your design.

TOPIC #2
Better PCB Design using the Fabricator’s View
What designers need to know about DFM verification and its impact on your design

SPEAKER
Ammar Abusham
Senior Applications Engineer
Mentor Graphics

PRESENTATION
You are an experienced PCB Designer using a good CAD flow. So why is it that what appears to be a good design to you and your layout tool, always seems to raise a bunch of questions with your fabricator?

Well, the fabricator sees things differently than you. If you’re like most designers, you are very focused on designing a PCB to the electrical and form-factor specifications. And of course, you take pride in how clean your design looks. Your fabricator on the other hand, is mostly paying attention to those aspects of your design which affect yield, costs, and delivery. To avoid any unpleasant surprises in these areas, it might make sense to put yourself in your fabricator’s shoes for a moment and see some of the checking they will perform on your design data prior to committing it to fabrication. To do this, we’re going to step through a typical PCB fabrication process and identify where Design for Manufacturability (DFM) issues are likely to show up and what the fabricator is looking for.

TOPIC
Advanced PCB Laminate Material Selection
What a designer needs to know about choosing the right material for your design

SPEAKER #1
Michael Gay
Director, High Performance Products
Isola Laminate Group

PRESENTATION
Designers are faced with many choices when trying to select the correct laminate type for your design. Many factors for performance, signal integrity, temperature range, microvia performance and cost come into play. Our speaker will share with us the various materials, properties and electrical characteristics to meet the requirements for your applications.

The presentation will cover various glass fabric and weave styles, resin technologies, pre-preg types, copper foil types and treatment properties. Also, he will discuss the many factors that influence the performance and signal integrity for high speed design applications. Other important information such as laminate thermal performance, guidance for understanding Data Sheet laminate properties, electrical properties and laminate cost considerations will be presented to increase your knowledge and stimulate your questions for our expert speaker.

SPEAKER #2
Dan Diesel
Chief Information Officer and Business Strategist
Insulectro

PRESENTATION
Designers are also faced with selecting the correct laminate type based on the material availability and the need for speed of delivery for the program. Our 2nd speaker will share what is being done in the market to continue to drive faster delivery speed and providing information to the designer regarding material availability and lead times.

TOPIC
PCB Routing Guidelines for Signal Integrity and Power Integrity, too

SPEAKER

Chris Heard
Signal Integrity Engineering Consultant
CSH Consulting, LLC

PRESENTATION
Recommendations to improve high speed performance of any design at any datarate
Our speaker has been deeply involved with Signal and Power Integrity for over 25 years and has a wealth of knowledge to share. Chris’s presentation will cover a list of "Do’s and Don'ts" regarding the most commonly seen routing practices that have big impacts on signal integrity. His presentation will cover the importance and signal integrity impact of drill size, pad size, antipad size, ground plane overhang, transition vias, AC Capacitors, skew compensation, backdrilling, blind vias, narrow versus wide lines and surface versus inner layer routing. Use of industry leading simulation tools will be presented.

In his presentation on Power Integrity, Chris will cover Voltage Drop and impedance response versus frequency for various power plane examples. The impact of various capacitor sizes and placement and the use of buried capacitor layers will be shown and discussed. The interaction and the understanding of these two disciplines are vital to success of the designer in achieving fully optimized designs. Don’t miss this opportunity to learn valuable tips from our expert speaker.

TOPIC
Embedded Passives
Learn the benefits of designing with internal resistors and capacitors

TOPIC
Routing Solutions
Strategies, Tools, and Techniques for Speeding up your Connections

SPEAKERS
Terri Kleekamp, CID

Applications Engineering Manager
Mentor Graphics
Xpedition Routing Technology Drives Strategy
Terri Kleekamp and Vern Wnek will introduce and demonstrate the routing strategies of Mentor’s Xpedition™ xPCB Layout, formerly known as Expedition PCB. Much more than just a name change, Terri will share with us Xpedition’s auto-assisted interactive routing technology and put it through its paces. Designers have always taken great pride in planning their designs, combining the needs of the engineers and manufacturers, into what we refer to as “artwork”. Xpedition now boasts a set of highly integrated automated routing features including the Sketch Router™, Hug Router, Real Trace Routing, and Dynamove. These tools facilitate an automated routing experience that includes intuitive user control, high quality, and exceptional performance in the hands of a designer.

John Carney

Staff Application Engineer
Cadence
Allegro Auto Interactive
John Carney from Cadence will be presenting their “Plan-Route-Optimize” strategies for routing in their Allegro tool. John will share their Route Planning tool which offers a fast and easy way to plan the routing of your design. He will share Auto-Interactive Breakout technology and demonstrate Allegro’s Auto Interactive routing features which include Auto-Interactive Delay tuning, phase tuning and Scribble mode routing, which allows you to ‘scribble’ a route path onto the canvas with one click the etch solution is generated. He will share Timing Vision, an innovative environment that allows you to graphically see real-time delay and phase information right on the routing canvas. Coupled with Auto-interactive Phase Tuning and Auto-interactive Delay Tuning capabilities, all of these routines improves the user experience and dramatically shortens the time required to develop a high-quality and effective routing solution.

Yan Killy, CID

Technical Marketing Engineer
PADS
PADS VX
Yan Killy will talk about Mentor Graphics continued investment in all routing technologies available in a PADS design flow. PADS continues to be the leader in Desk Top environment, delivering features and solutions to the PCB design community to solve ever challenging design task. Yan will talk about routing strategies and stage routing and present improvements in Constraint Management, Integrated Project and many other new technologies that help with the routing challenges engineers face. PADS interactive High Speed routing allows designers route critical nets to the rules specified. PADS Autorouting is a productivity enhancing tool, to finish simple and complex designs in fraction of time it will take to do it manually.

TOPIC #1
SPEED MATTERS

SPEAKER
Jim Ryan,
Product Manager
Insulectro

PRESENTATION
Shrink the turnaround time in fab by utilizing Z-axis conductive via paste technology
Insulectro supports the long held belief that SPEED MATTERS. This is true in PCB design as well as manufacturing. High Density Interconnects in PCBs have traditionally been done using electroplating. However, new technologies have pushed advanced design requirements such as; finer pitch BGA density, higher PCB layer counts resulting in greater aspect ratios for drilling and plating, and fine diameter vias. These all contribute to process challenges which can effect yields and open opportunities for new solutions. One of these is Z axis conductive via paste. These pastes are environmentally friendly lead free, highly conductive both electrically and thermally, and sinter at normal PCB laminating temperatures to form a strong intermetallic connection with the layer copper. This enabling technology eliminates through hole plating and many sequential lamination steps. The result - designers can realize more reliable circuit boards delivered quicker than ever.



TOPIC #2
eSurface

SPEAKER
Alex Richardson
VP Strategic Operations
eSurface

PRESENTATION
A new look at additive PCB processing for increasing circuit density and decreasing fab costs
eSurface is a new and disruptive technology that enables fast and efficient processing through an additive PCB fabrication technique. The technology affords greater yields with robust results in fine feature requirements used in HDI / fine pitch BGA applications. Utilizing a true covalent bond with the substrate, the technology meets or exceeds current industry standards. This new green, environment friendly process significantly reduces process steps and variabilities, reducing fabrication cycle times and improves cost structures. As finer features, creative high layer stack ups and board density seem to have pushed the print and etch capability threshold, eSurface opens new doors to volumetric efficiency and designs not currently feasible.

TOPIC
What a designer needs to know about making the transition to higher density designs

SPEAKER
Don Carron, CID
Director of Technology - Advanced Circuits

Don presented the best way and easy to understand “do’s and don’ts” when considering fine pitch BGAs and small components for your design and board layout. He suggested the best ways to keep costs down and reliability high with robust design elements. The best way to incorporate blind and buried vias structures, as well as via-in-pad with both mechanically-drilled and epoxy-filled vias and the newest HDI using laser microvias, copper filled and staggered or stacked structures were all presented. All with a focus on reliability, this was a highly interesting and informative presentation for PCB designers and engineers of all levels.

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